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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 1 1 publication order number: NCP3135/d NCP3135 5 a integrated synchronous buck converter NCP3135 is a fully integrated synchronous buck converter for 3.3 v and 5 v step?down applications. it can provide up to 5 a dc load and 6 a instantaneous load current. NCP3135 supports high efficiency, fast transient response and provides power good indicator. the control scheme includes two operation modes: fccm and automatic ccm/dcm. in automatic ccm/dcm mode, the controller can smoothly switch between ccm and dcm, where converter runs at reduced switching frequency with much higher efficiency. NCP3135 is available in 3 mm x 3 mm qfn?16 pin package . features ? high efficiency in both ccm and dcm ? high operation frequency at 1.1 mhz ? support mlcc output capacitor ? small footprint, 3 mm x 3 mm, 16?pin qfn package ? up to 5 a continuous output current ? 6 a instantaneous load current ? 2.9 v to 5.5 v wide conversion voltage range ? output voltage range from 0.6 v to 0.84 x vin ? internal 1 ms soft?start ? automatic power?saving mode ? voltage mode control ? support pre-bias start?up functionality ? output discharge operation ? over?t emperature protection ? built?in over?voltage, under?v oltage and over-current protection ? power good indicator ? this is a pb?free device applications ? 5 v step down rail ? 3.3 v step down rail qfn16 3 x 3, 0.5p case 485da marking diagram www. onsemi.com see detailed ordering, marking and shipping information in the package dimensions section on page 12 of this data sheet. ordering information suggested pin arrangement 16 15 1 2 67 5 14 13 12 8 11 10 9 3 4 pgnd pgnd vin vin en nc pgd vbst ps sw sw sw vdd agnd fb comp NCP3135 3135 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package 3135 alyw (note: microdot may be in either location) 1
NCP3135 www. onsemi.com 2 figure 1. block diagram + ? e/a vref ramp osc ss nc ps en comp fb pgd + agnd pgnd vdd sw vbst vin uvlo control logic & pwm logic power good, uvp, ovp, uvlo, overtemperature and vout discharge uvlo ocp drvh drvl table 1. pin description pin no. symbol description 1 en logic control to enabling the switcher. internally pulled up to vdd with a 1.35 m resistor 2 nc not connected 3 pgd open drain power good output 4 vbst gate drive voltage for high side fet. connect capacitor from this pin to sw 5, 6, 7 sw switch node between high?side mosfet and low?side mosfet 8 ps mode configuration pin (with 10 a current): pulled high or floating (internally pulled high): forced continuous conduction mode connect with resistor equal to or lower than ( )174 k to gnd: automatic ccm/dcm 9 comp output of the error amplifier 10 fb feedback pin. connect to resistor divider to set up the desired output voltage 11 agnd analog ground 12 vdd power supply input for control circuitry 13, 14 vin power input for power conversion and gate driver supply 15, 16 pgnd power ground
NCP3135 www. onsemi.com 3 figure 2. NCP3135 single voltage rail for v in and v dd 13 14 12 11 10 15 16 2 1 8 567 4 3 9 vin vin sw sw sw vdd agnd nc en ps pgnd pgnd comp fb pgd vbst NCP3135 en vin pgd vout c5 c6 c8 r6 r5 c4 l1 c7 c9 r7 c2 c3 r4 r3 c1 r1 r2 vin = 2.9 v 5.5 v figure 3. NCP3135 dual voltage rail for v in and v dd 13 14 12 11 10 15 16 2 1 8 567 4 3 9 vin vin sw sw sw vdd agnd nc en ps pgnd pgnd comp fb pgd vbst NCP3135 en vin pgd vout c5 c6 c8 r5 c4 l1 c7 c9 r7 c2 c3 r4 r3 c1 r1 r2 vin = 2.9 v 5.5 v v dd = 3.3 v
NCP3135 www. onsemi.com 4 table 2. absolute maximum ratings rating symbol value units min max input voltage range vin, vdd, ps, en ?0.3 6.5 v vbst ?0.3 17 vbst (with respect to sw) ?0.3 6.5 fb ?0.3 3.7 output voltage range sw dc ?1 6.5 v pulse < 20 ns, e = 5 j ?3 10 high?side fet and low?side fet drain? source voltage dc 6.5 ac, pulse < 50 ns 7.5 pgd ?0.3 6.5 comp ?0.3 6.5 pgnd ?0.3 0.3 operation ambient temperature t a ?40 125 c storage temperature t s ?55 150 junction temperature t j ?40 150 electrostatic discharge human body model (hbm) 2000 v charged device model (cdm) 500 lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 300 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 3. recommended operation ratings rating symbol value units min nom max input voltage range vin 2.9 5.5 v vdd 2.9 5.5 vbst ?0.1 13.5 vbst (with respect to sw) ?0.1 6 en ?0.1 3.5 fb, ps ?0.1 3.5 output voltage range sw ?1 6.5 v pgd ?0.1 6 comp ?0.1 3.5 pgnd ?0.1 0.1 junction temperature range, t j ?40 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. thermal information rating value units junction?to?ambient thermal resistance (note 1) 45 c/w 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja
NCP3135 www. onsemi.com 5 table 5. electrical characteristics (v dd = v in = 3.3 v and v dd = v in = 5.0 v, t a = t j = ?40 c to 125 c. typical values are at t a = 25 c, pgnd = gnd unless otherwise noted) parameter symbol test conditions min typ max units power supply vin operation voltage v in nominal input voltage range 2.9 5.5 v vin uvlo threshold ramp up; en = ?hi? 2.8 v vin uvlo hysteresis 130 mv vdd internal bias voltage nominal 3.3 v input voltage range 2.9 5.5 v vdd uvlo threshold ramp up; en = ?hi? 2.8 v vdd uvlo hysteresis 75 mv voltage monitor power good low voltage pull?down voltage with 4 ma sink current 200 400 mv power good high leakage current ?2.0 0 2.0 a power good threshold feedback lower voltage limit 80 83 86 %vref feedback higher voltage limit 114 117 120 %vref power good high delay t pgdelay 400 s minimum vin voltage for valid pgd at start up measured at vin with 1 ma (or 2 ma) sink current on pgd pin at start up 1 v output over - voltage protection threshold at fb 114 117 120 %vref over - voltage blanking time t ovpdly time from fb higher than 20% of vref to ovp fault 1.0 1.7 2.5 s output under - voltage protection threshold at fb 80 83 86 %vref under - voltage blanking time t uvpdly time from fb lower than 20% of vref to uvp fault 11 s supply current (t j = +25 c) vdd quiescent current i vdd en = ?hi?, no switching 2.2 3.5 ma vdd shutdown supply current i vdd_sd en = ?lo? 8.0 a vin shutdown supply current i qshdn en = ?lo?, vin = 5 v 3.5 a feedback voltage & error amplifier reference voltage at fb v ref ?40 c < t a < 85 c 594 600 606 mv unity gain bandwidth (note 1) 14 mhz open loop gain (note 1) 80 db fb pin leakage current 100 na output sourcing and sinking current (note 1) ccomp = 20 pf 5 ma slew rate (note 1) 5 v/ s over current protection & zero crossing over - current limit on high?side fet when iout exceeds this threshold for 4 consecutive cycles. vin = 3.3 v, vout = 1.5 v with 1 h inductor, t a = +25 c 6.9 7.2 8.1 a one time over - current latch off on the low?side fet immediately shut down when sensed cur- rent reach this value. vin = 3.3 v, vout = 1.5 v with 1 h inductor, t a = +25 c 7.0 8.1 a zero crossing comparator internal offset (note 1) pgnd?swn, automatic ccm/dcm mode ?4.5 ?3.0 ?1.5 mv
NCP3135 www. onsemi.com 6 table 5. electrical characteristics (v dd = v in = 3.3 v and v dd = v in = 5.0 v, t a = t j = ?40 c to 125 c. typical values are at t a = 25 c, pgnd = gnd unless otherwise noted) parameter units max typ min test conditions symbol logic pins: i/o voltage and current en high threshold voltage 1.1 1.18 1.30 v en hysteresis 0.18 0.24 v en input pull up resistor 1.35 m ps mode threshold voltage level 1 to level 2 2.2 v ps source 10 a pull?up current when enabled 8 10 12 a internal bst diode reverse?bias leakage current v bst = 6.6 v, v in = 3.3 v, t a = 25 c 1 a soft stop output discharge on?resistance en = 0, v in = 3.3 v, v out = 0.5 v 20 timers: soft start soft start ramp?up time t ss rising from vss = 0 v to vss = 0.6 v 1.0 ms delay after en asserting en = ?hi? 0.2 ms switching frequency control forced ccm mode 0.99 1.1 1.21 mhz pwm minimum off time fccm mode or automatic ccm/dcm mode 100 140 ns pwm ramp amplitude (note1) 2.9 v < v in < 5.5 v vin/4 v maximum duty cycle, fccm mode or automatic ccm/dcm mode fs w = 1.1 mhz, 0 c < t a < 85 c 84% 89% thermal shutdown thermal shutdown threshold (note 1) 130 140 150 c thermal shutdown hysteresis (note 1) 40 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. guaranteed by design, no production test
NCP3135 www. onsemi.com 7 typical characteristics figure 4. efficiency at auto ccm/dcm mode vin = 3.3 v figure 5. efficiency at fccm mode vin = 3.3 v output current (a) 5.0 2.5 2.0 1.5 1.0 0.5 0 80 82 86 88 90 94 96 98 figure 6. efficiency at auto ccm/dcm mode vin = 5.0 v figure 7. efficiency at fccm mode vin = 5.0 v figure 8. load regulation (output current vs. output voltage) figure 9. line regulation (input voltage vs. output voltage) output current (a) input voltage (v) 5.0 2.5 2.0 1.5 1.0 0.5 0 0 0.05 0.15 0.25 0.30 0.40 0.50 5.4 4.9 4.4 3.9 3.4 2.9 0 0.50 1.00 1.50 efficiency (%) output voltage change (%) output voltage change (%) 84 92 v out = 2.5 v 1.8 v 1.5 v 1.2 v 1.0 v output current (a) 5.0 2.5 2.0 1.5 1.0 0.5 0 80 82 86 88 90 94 96 98 efficiency (%) 84 92 v out = 2.5 v 1.8 v 1.5 v 1.2 v 1.0 v output current (a) 5.0 2.5 2.0 1.5 1.0 0.5 0 80 82 86 88 90 94 96 98 efficiency (%) 84 92 v out = 3.3 v 1.8 v 1.5 v 1.2 v 1.0 v output current (a) 5.0 2.5 2.0 1.5 1.0 0.5 0 80 82 86 88 90 94 96 98 efficiency (%) 84 92 v out = 3.3 v 1.8 v 1.5 v 1.2 v 1.0 v 0.25 0.75 1.25 vin = 5 v fccm vin = 5 v auto ccm/dcm vin = 3.3 v fccm and vin = 3.3 v auto ccm/dcm 1.5 v, 0 a, fccm 1.5 v, 0 a, auto ccm/dcm 3.0 3.5 4.0 4.5 3.0 3.5 4.0 4.5 3.0 3.5 4.0 4.5 2.5 v 2.5 v 3.0 3.5 4.0 4.5 3.0 3.5 4.0 4.5 0.10 0.20 0.35 0.45 1.5 v, 5 a, fccm 1.5 v, 5 a, auto ccm/dcm
NCP3135 www. onsemi.com 8 typical characteristics figure 10. switching frequency vs. output current at vin = 3.3 v figure 11. switching frequency vs. output current at vin = 5.0 v output current (a) 10 1 0.1 0.01 10 100 1000 10,000 figure 12. soft start?up at auto ccm/dcm mode vin = 3.3 v, no load figure 13. soft start?up at auto ccm/dcm mode vin = 3.3 v, 5 a load figure 14. pre?bias start?up at auto ccm/dcm mode vin = 3.3 v, no load figure 15. soft stop at auto ccm/dcm mode vin = 3.3 v, no load switching frequency (khz) vin = 3.3 v vout = 1.5 v fccm auto ccm/dcm output current (a) 10 1 0.1 0.01 10 100 1000 10,000 switching frequency (khz) fccm auto ccm/dcm en vout pgd en vout pgd en vout pgd vin = 5.0 v vout = 1.5 v pre?bias = 0.5 v en vout pgd
NCP3135 www. onsemi.com 9 typical characteristics figure 16. switching node waveform at auto ccm/dcm mode vin = 3.3 v, 5 a load figure 17. switching node waveform at auto ccm/dcm mode vin = 3.3 v, no load figure 18. switching node waveform at auto ccm/dcm mode vin = 5.0 v, 5 a load figure 19. switching node waveform at auto ccm/dcm mode vin = 5.0 v, no load
NCP3135 www. onsemi.com 10 detailed description overview NCP3135 is a low input voltage 5 a high performance synchronous buck converter with two integrated n?mosfets. NCP3135?s output voltage range is from 0.6 v to 0.84 x vin and it has wide input voltage range from 2.9 v to 5.5 v. the features of NCP3135 include supporting pre?bias start?up to protect sensitive loads, cycle?by?cycle over?current limiting and short circuit protection, power good monitor, over voltage and under voltage protection, built in output discharge and thermal shutdown. NCP3135 provides two operation modes to fit various application requirements. the automatic ccm/dcm mode operation provides reduced power loss and increases the efficiency at light load. the adaptive power control architecture enables smooth transition between light load and heavy load while maintaining fast response to load transients . operation mode NCP3135 of fers two operation modes programmed by ps pin connections, see table below. table 6. ps pin connection operation mode auto skip at light load ( )174 k to gnd automatic ccm/dcm yes floating or pulled to vdd fccm in forced continuous conduction mode (fccm), the high?side fet is on during the on?time and the low?side fet is on during the off?time. the switching is synchronized to an internal clock thus the switching frequency is fixed. in automatic ccm/dcm mode, the high?side fet is on during the on?time and low?side fet is on during the off?time until the inductor current reaches zero. an internal zero?crossing comparator detects the zero crossing of the inductor current from positive to negative. when the inductor current reaches zero, the comparator sends a signal to the logic circuitry and turns off the low?side fet. when the load is increased, the inductor current is always positive and the zero?crossing comparator does not send any zero?crossing signal. the converter enters into continuous conduction mode (ccm) when no zero?crossing is detected for two consecutive pwm pulses. in ccm mode, the switching synchronizes to the internal clock and the switching frequency is fixed. reference voltage the NCP3135 incorporates 600 mv reference voltage with 1.0 % tolerance. internal soft?start to limit the start?up inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 v to its final value linearly. the internal soft start time is 1.0 ms typically. soft stop soft?stop or discharge mode is always on during faults or disable. in this mode, disable (en) causes the output to be discharged through an internal 2 0 transistor inside of sw terminal. the time constant of soft?stop is a function of output capacitance and the resistance of the discharge transistor. automatic power saving mode in automatic ccm/dcm mode when the load current decreases, the converter will enter power saving mode operation. during power saving mode, the low?side mosfet will turn off when the inductor current reaches zero. so the converter skips switching and operates with reduced frequency , which minimizes the quiescent current and maintains high efficiency. forced continuous conduction mode when ps pin is floating or pulled high, NCP3135 is operating in forced continuous conduction mode in both light load and heavy load conditions. in this mode, the switching frequency remains constant over the entire load range, making it suitable for applications that need tight regulation of switching frequency at a cost of lower efficiency at light load.
NCP3135 www. onsemi.com 11 protections under voltage lockout (uvlo) there is under - voltage lock out protection (uvlo) for both vin and vdd in NCP3135, which has a typical trip threshold voltage 2.8 v and trip hysteresis 75 mv for vdd and 130 mv for vin. if uvlo is triggered, the device resets and waits for the voltage to rise up over the threshold voltage and restart the part. please note this protection function does not trigger the fault counter to latch off the part. over voltage protection (ovp) when feedback voltage is above 17% (typical) of nominal voltage for over 1.7 s blanking time, an ov fault is set. in this case, the converter de?asserts the pgd signal and performs the over?voltage protection function. the top gate drive is turned off and the bottom gate drive is turned on to discharge the output. the bottom gate drive will be turned off until vfb drops below the uvp threshold. the device enters a high?impedance state. this protection is latched. under voltage protection (uvp) output under?voltage protection works in conjunction with the current protection described in the over?current protection sections. an uvp circuit monitors the feedback voltage to detect under?voltage event. the under?voltage limit is 17% (typical) below of nominal voltage at fb pin. if the feedback voltage is below this threshold over 11 s, an uv fault is set and both the high?side and the low?side fets turn off . this protection is latched. power good monitor (pgd) NCP3135 provides window comparator to monitor the output voltage at fb pin. when the output voltage is within 17% of regulation voltage, the power good pin outputs a high signal. otherwise, pgd stays low. the pgd pin is open drain 5 ma pull down output. during startup, pgd stays low until the feedback voltage is within the specified range for about 0.4 ms. if feedback voltage falls outside the tolerance band, the pg pin goes low after 10 s delay . the pgd pin de?asserts as soon as the en pin is pulled low or an under?voltage event on vdd is detected. over current protection (ocp) NCP3135 provides both high?side and low?side mosfet current limiting. when the current through the high?side fet exceeds 7.5 a, the high?side fet turns off and the low?side fet turns on until next pwm cycle. an over?current counter is triggered and starts to increment each occurrence of an over?current event. both the high?side and the low?side fets turn off when the oc counter reaches four. the oc counter resets if the detected current is less than 7.5 a after an oc event. another set of over?current circuitry monitors the current flowing through the low?side fet. if the current through the low?side fet exceeds 8.1 a, the over?current protection is enabled and immediately turns off both the high?side and the low?side fets. the device is fully protected against over?current during both on?time and off?time. this protection is latched. pre?bias startup in some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 v to just below the regulation voltage. this situation occurs for a number of reasons: the converter?s output capacitors may have residual charge on them or the converter?s output may be held up by a low current standby power supply . NCP3135 supports pre?bias start up by holding low?side fets off until soft start ramp reaches the fb pin voltage. thermal shutdown the NCP3135 protects itself from over heating with an internal thermal monitoring circuit. when the die temperature g oes beyond a threshold value 135 c, both the high?side and the low?side fets turn off until the temperature falls 40 c below of the threshold value. then the converter restarts. application note for higher output voltage application cases (vout = 3.3 v), choose the inductor value not to be lower than 1 h to avoid over-current protection being triggered by inductor current ripple; for vin = 5 v and vout = 3.3 v case, add a voltage divider between vin and en to ensure that the part can start up without triggering uvp. use figure 20 as design reference for schematics. for other lower output voltage cases, it is not necessary to add this divider. figure 20. voltage divider between vin and en for start?up in vin = 5 v and vout = 3.3 v case v in = 5 v 10 k 3.6 k en pgnd
NCP3135 www. onsemi.com 12 layout guidelines when laying out a power pcb for the NCP3135 there are several key points to consider. use four vias to connect the thermal pad to power ground. separate the power ground and analog ground planes; connect them together at a single point. increase the thickness of pcb copper, it can help to lower the die temperature and improve the overall efficiency but meanwhile increase the cost of the board fabrication. use wide traces for the nodes conducting high current such as vin, vout, pgnd and sw. place feedback and compensation network components close to the ic. keep fb, comp away from noisy signals such as sw, bst. place vin and vdd decoupling capacitors as close to the ic as possible. ordering information device marking package shipping ? NCP3135mntxg 3135 qfn16, 3 x 3, 0.5p (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP3135 www. onsemi.com 13 package dimensions qfn16 3x3, 0.5p case 485da issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.05 c 0.05 a1 seating plane e/2 16x note 3 b 16x 0.10 c 0.05 c a b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 b 0.20 0.30 d 3.00 bsc d2 1.55 1.75 e 3.00 bsc e2 1.55 1.75 e 0.50 bsc l 0.30 0.50 5 9 1 16 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.78 3.30 dimensions: millimeters 0.61 16x note 4 0.30 16x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions l ??? ??? 0.00 0.15 outline package e recommended k 0.275 ref l2 0.09 ref 1 1.78 3.30 l2 8x 0.10 c a b 0.10 c a b k on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP3135/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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